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1 ? fn8183.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas, inc. copyright intersil americas inc. 2004-2005, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. x9317 low noise, low power, 100 taps digitally controlled potentiometer (xdcp?) the intersil x9317 is a digitally controlled potentiometer (xdcp?). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface. the potentiometer is implemen ted by a resistor array composed of 99 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. pinouts x9317 (8 ld tssop) top view x9317 (8 ld pdip, 8 ld soic, 8 ld msop) top view features ? solid-state potentiometer ? 3-wire serial up/down interface ? 100 wiper tap points - wiper position stored in nonvolatile memory and recalled on power-up ? 99 resistive elements - temperature compensated - end-to-end resistance range 20% ? low power cmos -v cc = 2.7v to 5.5v, and 5v 10% - standby current <1a ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ?r total values = 1k , 10k , 50k , 100k ? packages - 8 ld soic, pdip, tssop, and msop ? pb-free available (rohs compliant) applications ? lcd bias control ? dc bias adjustment ? gain and offset trim ? laser diode bias control ? voltage regulator output control inc r l cs v cc 1 2 3 4 8 7 6 5 x9317 u/d r w v ss r h r h v cc inc u/d 1 2 3 4 8 7 6 5 x9317 v ss cs r l r w data sheet june 25, 2008
2 fn8183.4 june 25, 2008 ordering information part number part marking v cc limits (v) r total (k ) temperature range (c) package pkg. dwg. # x9317zm8* afg 5 10% 1 0 to +70 8 ld msop m8.118 x9317zm8z* (note) dda 0 to +70 8 ld msop (pb-free) m8.118 x9317zm8i* afi -40 to +85 8 ld msop m8.118 x9317zm8iz* (note) dcy -40 to +85 8 ld msop (pb-free) m8.118 x9317zp x9317zp 0 to +70 8 ld pdip mdp0031 x9317zs8* x9317z 0 to +70 8 ld soic mdp0027 x9317zs8z* (note) x9317z z 0 to +70 8 ld soic (pb-free) mdp0027 x9317zs8i* x9317z i -40 to +85 8 ld soic mdp0027 x9317zs8iz* (note) x9317z z i -40 to +85 8 ld soic (pb-free) mdp0027 x9317zv8* 9317z 0 to +70 8 ld tssop m8.173 x9317zv8z* (note) 9317z z 0 to +70 8 ld tssop (pb-free) m8.173 x9317zv8i* 317z i -40 to +85 8 ld tssop m8.173 x9317zv8iz* (note) 9317z iz -40 to +85 8 ld tssop (pb-free) m8.173 x9317wm8* abf 10 0 to +70 8 ld msop m8.118 x9317wm8z* (note) dcw 0 to +70 8 ld msop (pb-free) m8.118 x9317wm8i* ads -40 to +85 8 ld msop m8.118 x9317wm8iz* (note) dct -40 to +85 8 ld msop (pb-free) m8.118 x9317wp x9317wp 0 to +70 8 ld pdip mdp0031 x9317wpi x9317wp i -40 to +85 8 ld pdip mdp0031 x9317ws8* x9317w 0 to +70 8 ld soic mdp0027 x9317ws8z* (note) x9317w z 0 to +70 8 ld soic (pb-free) mdp0027 x9317ws8i* x9317w i -40 to +85 8 ld soic mdp0027 x9317ws8iz* (note) x9317w zi -40 to +85 8 ld soic (pb-free) mdp0027 x9317wv8*, ** 9317w 0 to +70 8 ld tssop m8.173 x9317wv8z* (note) 9317w z 0 to +70 8 ld tssop (pb-free) m8.173 x9317wv8i* 317w i -40 to +85 8 ld tssop m8.173 x9317wv8iz* (note) 9317w iz -40 to +85 8 ld tssop (pb-free) m8.173 x9317um8* aec 50 0 to +70 8 ld msop m8.118 x9317um8z* (note) dcs 0 to +70 8 ld msop (pb-free) m8.118 x9317um8i* afe -40 to +85 8 ld msop m8.118 x9317um8iz* (note) dcr -40 to +85 8 ld msop (pb-free) m8.118 x9317up x9317up 0 to +70 8 ld pdip mdp0031 x9317upi x9317up i -40 to +85 8 ld pdip mdp0031 x9317us8* x9317u 0 to +70 8 ld soic mdp0027 x9317us8z* (note) x9317u z 0 to +70 8 ld soic (pb-free) mdp0027 x9317us8i* x9317u i -40 to +85 8 ld soic mdp0027 x9317us8iz* (note) x9317u zi -40 to +85 8 ld soic (pb-free) mdp0027 x9317uv8* 9317u 0 to +70 8 ld tssop m8.173 x9317uv8z* (note) 9317u z 0 to +70 8 ld tssop (pb-free) m8.173 x9317uv8i* 317u i -40 to +85 8 ld tssop m8.173 x9317uv8iz* (note) 9317u iz -40 to +85 8 ld tssop (pb-free) m8.173 x9317
3 fn8183.4 june 25, 2008 x9317tm8*, ** agd 5 10% 100 0 to +70 8 ld msop m8.118 x9317tm8z* (note) dcn 0 to +70 8 ld msop (pb-free) m8.118 x9317tm8i*, ** agf -40 to +85 8 ld msop m8.118 x9317tm8iz* (note) dcl -40 to +85 8 ld msop (pb-free) m8.118 x9317tp x9317tp 0 to +70 8 ld pdip mdp0031 x9317tpi x9317tp i -40 to +85 8 ld pdip mdp0031 x9317ts8 x9317t 0 to +70 8 ld soic mdp0027 x9317ts8z (note) x9317t z 0 to +70 8 ld soic (pb-free) mdp0027 x9317ts8i x9317t i -40 to +85 8 ld soic mdp0027 x9317ts8iz (note) x9317t zi -40 to +85 8 ld soic (pb-free) mdp0027 x9317tv8*, ** 9317t 0 to +70 8 ld tssop m8.173 x9317tv8z* (note) 9317t z 0 to +70 8 ld tssop (pb-free) m8.173 x9317tv8i*, ** 317t i -40 to +85 8 ld tssop m8.173 x9317tv8iz* (note) 9317t iz -40 to +85 8 ld tssop (pb-free) m8.173 x9317zm8-2.7* afh 2.7 to 5.5 1 0 to +70 8 ld msop m8.118 x9317zm8z-2.7* (note) aoa 0 to +70 8 ld msop (pb-free) m8.118 x9317zm8i-2.7* afj -40 to +85 8 ld msop m8.118 x9317zm8iz-2.7* (note) dcz -40 to +85 8 ld msop (pb-free) m8.118 x9317zs8-2.7* x9317z f 0 to +70 8 ld soic mdp0027 x9317zs8z-2.7* (note) x9317z zf 0 to +70 8 ld soic (pb-free) mdp0027 x9317zs8i-2.7* x9317z g -40 to +85 8 ld soic mdp0027 x9317zs8iz-2.7* (note) x9317z zg -40 to +85 8 ld soic (pb-free) mdp0027 x9317zv8-2.7* 317z f 0 to +70 8 ld tssop m8.173 x9317zv8z-2.7* (note) 9317z fz 0 to +70 8 ld tssop (pb-free) m8.173 x9317zv8i-2.7*, ** 317z g -40 to +85 8 ld tssop m8.173 x9317zv8iz-2.7* (note) 9317z gz -40 to +85 8 ld tssop (pb-free) m8.173 x9317wm8-2.7* acz 10 0 to +70 8 ld msop m8.118 x9317wm8z-2.7* (note) dcx 0 to +70 8 ld msop (pb-free) m8.118 x9317wm8i-2.7* adt -40 to +85 8 ld msop m8.118 x9317wm8iz-2.7* dcu -40 to +85 8 ld msop (pb-free) m8.118 x9317wp-2.7 x9317wp f 0 to +70 8 ld pdip mdp0031 x9317wpi-2.7 x9317wp g -40 to +85 8 ld pdip mdp0031 x9317ws8-2.7* x9317w f 0 to +70 8 ld soic mdp0027 x9317ws8z-2.7* (note) x9317w zf 0 to +70 8 ld soic (pb-free) mdp0027 x9317ws8i-2.7*, ** x9317w g -40 to +85 8 ld soic mdp0027 x9317ws8iz-2.7* (note) x9317w zg -40 to +85 8 ld soic (pb-free) mdp0027 x9317wv8-2.7* 317w f 0 to +70 8 ld tssop m8.173 x9317wv8z-2.7* (note) 9317w fz 0 to +70 8 ld tssop (pb-free) m8.173 x9317wv8i-2.7*, ** 317w g -40 to +85 8 ld tssop m8.173 x9317wv8iz-2.7* (note) akz -40 to +85 8 ld tssop (pb-free) m8.173 ordering information (continued) part number part marking v cc limits (v) r total (k ) temperature range (c) package pkg. dwg. # x9317
4 fn8183.4 june 25, 2008 x9317um8-2.7* aed 2.7 to 5.5 10 0 to +70 8 ld msop m8.118 x9317um8z-2.7* (note) aob 0 to +70 8 ld msop (pb-free) m8.118 x9317um8i-2.7*, ** aff -40 to +85 8 ld msop m8.118 x9317um8iz-2.7* (note) aoh -40 to +85 8 ld msop (pb-free) m8.118 x9317us8-2.7* x9317u f 50 0 to +70 8 ld soic mdp0027 x9317up-2.7 x9317up f 0 to +70 8 ld pdip mdp0031 x9317upi-2.7 x9317up g -40 to +85 8 ld pdip mdp0031 x9317us8z-2.7* (note) x9317u zf 0 to +70 8 ld soic (pb-free) mdp0027 x9317us8i-2.7*, ** x9317u g -40 to +85 8 ld soic mdp0027 x9317us8iz-2.7* (note) x9317u zg -40 to +85 8 ld soic (pb-free) mdp0027 x9317uv8-2.7* 317u f 0 to +70 8 ld tssop m8.173 x9317uv8z-2.7* (note) 9317u fz 0 to +70 8 ld tssop (pb-free) m8.173 x9317uv8i-2.7*, ** 317u g -40 to +85 8 ld tssop m8.173 x9317uv8iz-2.7* (note) 9317u gz -40 to +85 8 ld tssop (pb-free) m8.173 x9317tm8-2.7*, ** age 100 0 to +70 8 ld msop m8.118 x9317tm8z-2.7* (note) dcp 0 to +70 8 ld msop (pb-free) m8.118 x9317tm8i-2.7*, ** agg -40 to +85 8 ld msop m8.118 x9317tm8iz-2.7* (note) dcm -40 to +85 8 ld msop (pb-free) m8.118 x9317tp-2.7 x9317tp f 0 to +70 8 ld pdip mdp0031 x9317tpi-2.7 x9317tp g -40 to +85 8 ld pdip mdp0031 x9317ts8-2.7*, ** x9317t f 0 to +70 8 ld soic mdp0027 x9317ts8z-2.7* (note) x9317t zf 0 to +70 8 ld soic (pb-free) mdp0027 x9317ts8i-2.7*, ** x9317t g -40 to +85 8 ld soic mdp0027 x9317ts8iz-2.7* (note) x9317t zg -40 to +85 8 ld soic (pb-free) mdp0027 x9317tv8-2.7*, ** 317t f 0 to +70 8 ld tssop m8.173 x9317tv8z-2.7* (note) 9317t fz 0 to +70 8 ld tssop (pb-free) m8.173 x9317tv8i-2.7*, ** 317t g -40 to +85 8 ld tssop m8.173 x9317tv8iz-2.7* (note) 9317t gz -40 to +85 8 ld tssop (pb-free) m8.173 note: these intersil pb-free plas tic packaged products employ special pb-free mate rial sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. *add "t1" suffix for tape and reel. please refer to tb347 for details on reel specifications. **add "t2" suffix for tape and reel. please refe r to tb347 for details on reel specifications. ordering information (continued) part number part marking v cc limits (v) r total (k ) temperature range (c) package pkg. dwg. # x9317
5 fn8183.4 june 25, 2008 block diagram up/down counter 7-bit nonvolatile memory store and recall control circuitry one of one decoder resistor array r h u/d inc cs wiper switches hundred v cc v ss r l r w control and memory up/down (u/ d ) increment ( inc ) device select ( cs ) v cc (supply voltage) v ss (ground) r h r w r l general detailed 0 1 2 96 97 98 99 pin descriptions pdip/soic/msop tssop symbol brief description 13inc increment . toggling inc while cs is low moves the wiper either up or down. 24u/d up/down . the u/d input controls the direction of the wiper movement. 35r h the high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 46v ss ground. 57r w the wiper terminal is equivalent to the mova ble terminal of a mechanical potentiometer. 68 r l the low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 71cs chip select . the device is selected when the cs input is low, and de-selected when cs is high. 82v cc supply voltage. x9317
6 fn8183.4 june 25, 2008 absolute maximum rati ngs thermal information i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8ma r h , r w , r l to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v voltage on cs , inc , u/d and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v junction temperature under bias . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. potentiometer specifications v cc = full range, t a = full operating temperature range, unless otherwise stated. symbol parameter test conditions/notes min (note 8) typ (note 4) max (note 8) unit r total end-to-end resistance tolerance see ?ordering information? beginning on page 2 for values -20 +20 % v rh / rl r h /r l terminal voltage v ss = 0v v ss v cc v power rating r total 10k 10 mw r total = 1k 25 mw r w wiper resistance i w = 1ma, v cc = 5v 200 400 i w = 1ma, v cc = 2.7v 400 1000 i w wiper current (note 5) see ?test circuit? on page 7 -4.4 +4.4 ma noise (note 7) ref: 1khz -120 dbv resolution 1% absolute linearity (note 1) v(r h ) = v cc , v(r l ) = 0v -1 +1 mi (note 3) relative linearity (note 2) v(r h ) = v cc , v(r l ) = 0v -0.2 +0.2 mi (note 3) r total temperature coefficient (note 5) v(r h ) = v cc , v(r l ) = 0v 300 ppm/c ratiometric temperature coefficient (notes 5, 6) v(r h ) = v cc , v(r l ) = 0v -20 +20 ppm/c c h /c l /c w (note 5) potentiometer capacitances see ?equivalent circuit? on page 7 10/10/25 pf v cc supply voltage x9317 4.5 5.5 v x9317-2.7 2.7 5.5 v dc electrical specifications v cc = 5v 10%, t a = full operating temperature range, unless otherwise stated. symbol parameter test conditions min (note 8) typ (note 4) max (note 8) unit i cc1 v cc active current (increment) cs = v il , u/d = v il or v ih and inc =v il /v ih @ min. t cyc r l , r h , r w not connected 50 a i cc2 v cc active current (store) (non-volatile write) cs = v ih , u/d = v il or v ih and inc = v il or v ih . r l , r h , r w not connected 400 a i sb standby supply current cs v ih , u/d and inc =v il r l , r h , r w not connected 1a i li cs , inc , u/d input leakage current v in = v ss to v cc -10 +10 a v ih cs , inc , u/d input high voltage v cc x 0.7 v cc + 0.5 v v il cs , inc , u/d input low voltage -0.5 v cc x 0.1 v c in (note 5) cs , inc , u/d input capacitance v cc = 5v, v in = v ss , t a = +25c, f=1mhz 10 pf x9317
7 fn8183.4 june 25, 2008 endurance and data retention v cc = 5v 10%, t a = full operating temperature range. parameter min unit minimum endurance 100,000 data changes per bit data retention 100 years notes: 1. absolute linearity is utilized to determine ac tual wiper voltage versus expected voltage = [v(r w(n)(actual) )-v(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/99 + v(r l ), with n from 0 to 99. 2. relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )-(v(r w(n) ) - mi)]/mi. 3. 1 ml = minimum increment = [v(r h )-v(r l )]/99. 4. typical values are for t a = +25c and nominal supply voltage. 5. this parameter is not 100% tested. 6. ratiometric temperature coefficient = (v(r w ) t1(n) -v(r w ) t2(n) )/[v(r w ) t1(n) (t1-t2) x 10 6 ], with t1 and t2 being 2 temperatures, and n from 0 to 99. 7. measured with wiper at tap position 99, r l grounded, using test circuit. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. test circuit equivalent circuit force current test point r w c h c l r w 10pf 10pf r total c w 25pf r h r l ac conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v ac electrical specifications v cc = 5v 10%, t a = full operating temperature range, unless otherwise stated. symbol parameter min (note 8) typ (note 4) max (note 8) unit t cl cs to inc setup 50 ns t ld (note 5) inc high to u/d change 100 ns t di (note 5) u/d to inc setup 1 s t ll inc low period 960 ns t lh inc high period 960 ns t lc inc inactive to cs inactive 1 s t cphs cs deselect time (store) 10 ms t cphns (note 5) cs deselect time (no store) 100 ns t iw inc to r w change 1 5 s t cyc inc cycle time 2 s t r , t f (note 5) inc input rise and fall time 500 s t pu (note 5) power-up to wiper stable 5s t r v cc (note 5) v cc power-up rate 0.2 50 v/ms t wr store cycle 510ms x9317
8 fn8183.4 june 25, 2008 power-up and down requirements the recommended power-up sequence is to apply v cc /v ss first, then the potentiometer voltages. during power-up, the data sheet parameters for the dcp do not fully apply until 1ms after v cc reaches its final value. the v cc ramp spec is always in effect. in order to prevent unwanted tap position changes, or an inadvertent store, bring the cs and inc high before or concurrently with the v cc pin on power-up. ac timing typical performance characteristic cs inc u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns -55 -350 -300 -250 -200 -150 -100 -50 0 -45 -35 -25 -15 -5 5 15 25 35 temperature (c) ppm 45 55 65 75 85 95 105115 125 figure 1. typical total resistance temperature coefficient x9317
9 fn8183.4 june 25, 2008 pin descriptions r h and r l the high (r h ) and low (r l ) terminals of the x9317 are equivalent to the fixed terminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. the position of the wiper within the array is determined by the control inputs. the wiper terminal series resistance is typically 200 . up/down (u/d ) the u/d input controls the direction of the wiper movement and whether the counter is incremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the u/d input. chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is complete, the x9317 will be placed in the low power standby mode until the device is selected once again. pin configuration principles of operation there are three sections of th e x9317: the control section, the nonvolatile memory, and the resistor array. the control section operates just like an up /down counter. the output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. the contents of the counter ca n be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 99 individual resistors connected in series. electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, r w . the wiper acts like its mechanical equivalent and does not move beyond the first or last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low, the device is selected and enabled to respond to the u/d and inc inputs. high to low transitions on inc will increment or decrement (depending on the state of the u/d input) a 7-bit counter. the output of this c ounter is decoded to select one of one hundred wiper positions along the resistive array. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. r h v cc inc u/d 1 2 3 4 8 7 6 5 x9317 dip/soic/msop v ss cs r l r w inc r l cs v cc 1 2 3 4 8 7 6 5 x9317 tssop u/d r w v ss r h pin names symbol description r h high terminal r w wiper terminal r l low terminal v ss ground v cc supply voltage u/d up/down control input inc increment control input cs chip select control input x9317
10 fn8183.4 june 25, 2008 the system may select the x9317, move the wiper and deselect the device without havi ng to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as previously described and once the new position is reached, t he system must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or until a power-up/down cycle recalls the previously stored data. this procedure allows the syst em to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjust ments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. applications information electronic digitally controlled (xdcp) potentiometers provide three powerful application advantages: 1. the variability and reliability of a solid-state potentiometer, 2. the flexibility of computer -based digital controls, and 3. the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. mode selection cs inc u/d mode l h wiper up l l wiper down h x store wiper position to nonvolatile memory h x x standby l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) x9317
11 fn8183.4 june 25, 2008 basic configurations of electronic potentiometers basic circuits v ref r w v ref i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current r h r l cascading techniques buffered reference voltage - + +5v r 1 +v v ref v out lmc7101 r w r w +v +v +v x (a) (b) v out = v w /r w single supply inverting amplifier voltage regulator r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 offset voltage adjustment + - v s v o r 2 r 1 100k 10k 10k 10k +5v lmc7101 comparator with hysteresis v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) + - r 1 v o lmc7101 + - v s v o r 2 r 1 } lt311a +5v r 2 +5v 100k 100k +5v v s v o = (r2/r1)v s r w } x9317
12 fn8183.4 june 25, 2008 x9317 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
13 fn8183.4 june 25, 2008 x9317 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m8.173 8 lead thin shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n8 87 0 o 8 o 0 o 8 o - rev. 1 12/00
14 fn8183.4 june 25, 2008 x9317 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8183.4 june 25, 2008 x9317 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c

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